A Unified Physics-Aware Quantum Machine Learning Framework across Power GaN HEMTs and Logic Nanowire FETs: Predicting Unseen Process Splits and Held-Out Geometry Combinations with Lower Error and Tighter Split-to-Split Variability
A reinforcement-learning framework discovers compact parametrized quantum circuits for data-scarce device modeling. A graph neural network policy optimized by proximal policy optimization searches circuit architectures using leave-one-group-out cross-validation error on held-out process or geometry groups as the reward. The framework achieves the lowest mean absolute error on all 11 targets versus six classical baselines, with 59% lower error (Ioff) and 81% tighter fold variability (VTH) for HEMTs and 84% lower error (VTH, SS, Ioff) and 82% tighter fold variability (Ioff) for NWFETs.
Researchers present a unified reinforcement-learning framework that discovers compact parametrized quantum circuits for data-scarce device modeling. A graph neural network policy optimized by proximal policy optimization searches circuit architectures using leave-one-group-out cross-validation error on held-out process or geometry groups as the reward. The framework achieves the lowest mean absolute error on all 11 targets versus six classical baselines, with 59% lower error (Ioff) and 81% tighter fold variability (VTH) for HEMTs and 84% lower error (VTH, SS, Ioff) and 82% tighter fold variability (Ioff) for NWFETs. These results demonstrate the potential of RL-selected, classically simulated PQCs as compact surrogates with low out-of-distribution error and improved physical consistency, despite imposing no explicit physical constraints, penalty terms, or device-specific equations, on the two evaluated device datasets.
The framework uses a GNN policy trained with PPO to search for parametrized quantum circuit architectures, with LOGOCV error on held-out groups as reward. It outperforms six classical baselines on all 11 targets, achieving 59% lower error for Ioff and 81% tighter fold variability for VTH on HEMTs, and 84% lower error for VTH, SS, Ioff and 82% tighter fold variability for Ioff on NWFETs. The approach requires no explicit physical constraints or device-specific equations, yet yields improved physical consistency.
This research suggests that RL-selected quantum circuits could serve as compact, data-efficient surrogates for semiconductor device modeling, potentially reducing the need for large datasets and enabling faster process development. The demonstrated improvements in out-of-distribution error and variability could translate to more reliable predictions for unseen process splits and geometry combinations in power and logic devices.
The framework could lower modeling costs and time-to-insight for semiconductor companies by reducing data requirements and improving prediction accuracy for new process conditions. It may enable faster exploration of device design spaces and more robust yield prediction, with potential applications in power electronics and advanced logic nodes.
Next observable signals include validation on additional device types or fabrication datasets, comparison with other quantum or hybrid classical-quantum surrogates, and exploration of hardware deployment of the discovered circuits. If the approach scales, it may influence design-technology co-optimization workflows and accelerate technology development cycles.