NAS-Driven Hardware Accelerator Exploration for Edge AI and Quantization Effects on the Pareto Space
A paper proposes a three-stage pipeline: a hardware-agnostic Pareto rank surrogate frontend on NAS-Bench-201, a quantization bridge with Pareto-aware filtering and feedback control, and an evolutionary Domain Space Exploration backend on CGRA4ML. It empirically characterizes how INT4 Post-Training Quantization perturbs the NAS-Bench-201 Pareto space using formal stability metrics on all 15,625 architectures.
Edge AI deployment requires neural architectures that balance accuracy, computational efficiency, and hardware deployability. Hardware-aware Neural Architecture Search (NAS) addresses this, but recent works that incorporate quantization into the NAS loop increase search complexity and tightly couple architecture and quantization design. This paper focuses on the less-studied post-search quantization strategy. It proposes a three-stage pipeline: a hardware-agnostic Pareto rank surrogate frontend on NAS-Bench-201, a quantization bridge with Pareto-aware filtering and feedback control, and an evolutionary Domain Space Exploration (DSE) backend on CGRA4ML for optimal hardware mapping. Additionally, it empirically characterizes how INT4 Post-Training Quantization (PTQ) perturbs the NAS-Bench-201 Pareto space through formal stability metrics on ground-truth data for all 15,625 architectures.
The paper introduces a formal stability metric to quantify how INT4 PTQ shifts the Pareto frontier of NAS-Bench-201 architectures. The three-stage pipeline decouples architecture search, quantization, and hardware mapping, potentially reducing search complexity compared to quantization-aware NAS. The use of CGRA4ML as the DSE backend suggests a focus on reconfigurable accelerators, which may offer flexibility for quantized models.
This research addresses a practical gap in edge AI deployment: understanding how post-training quantization affects the set of optimal architectures found by NAS. By providing a framework that combines quantized architecture mapping with automated hardware exploration, it could streamline the design of efficient edge AI systems. The focus on INT4 quantization aligns with industry trends toward low-precision inference for resource-constrained devices.
For companies deploying AI on edge devices, this work could reduce the time and cost of finding hardware-efficient, quantized neural architectures. The decoupled pipeline may enable faster design cycles and better hardware utilization, potentially lowering inference costs and power consumption. The framework could be valuable for semiconductor companies designing AI accelerators and for edge AI software vendors.
Next signals to watch include: (1) whether the proposed pipeline is validated on real hardware beyond simulation; (2) adoption of the stability metrics by other NAS researchers; (3) extension to other quantization schemes (e.g., INT8, mixed-precision) and NAS benchmarks; (4) integration with commercial edge AI toolchains. The paper's arXiv preprint status suggests peer-reviewed publication may follow.