On Synthesis of Metric Interval Temporal Logics
A paper titled 'On Synthesis of Metric Interval Temporal Logics' was published on arXiv on 2026-09-01. It presents a framework for precise passive learning of Metric Interval Temporal Logic (MITL) specifications without predefined templates or restricted fragments. The approach reduces timed learning to untimed learning by injecting timing constraints as Boolean atomic propositions, enabling use of off-the-shelf LTL tools. The framework is complete, guaranteeing a separating specification can always be found. Evaluation on benchmarks demonstrates effectiveness.
The paper introduces the first framework for precise passive learning of Metric Interval Temporal Logic (MITL) specifications, avoiding predefined templates or restricted fragments. It reduces the timed learning problem to a scalable untimed one by identifying quantitative timing differences between positive and negative traces, synthesizing precise timed constraints, and injecting them as new Boolean atomic propositions. This embeds timing into the alphabet, allowing complex formula evaluation to be delegated to highly optimized, off-the-shelf untimed LTL tools. The framework is complete, guaranteeing a separating specification can always be found. Evaluation across several benchmarks demonstrates the approach's effectiveness.
The key technical contribution is a reduction from timed specification mining to untimed LTL learning by encoding timing constraints as Boolean propositions. This leverages mature LTL tooling and avoids the complexity of direct MITL synthesis. The completeness guarantee is notable, ensuring a separating specification exists for any learnable set of traces. The approach is evaluated on benchmarks, though specific metrics are not provided in the evidence.
Automated mining of formal specifications is critical for verifying real-time systems, which are prevalent in automotive, aerospace, and industrial control. This framework could lower the barrier to adopting formal methods by enabling passive learning of expressive timed properties from execution traces, potentially improving reliability and reducing manual specification effort.
The framework could be valuable for companies developing safety-critical real-time systems, as it automates the extraction of formal timing specifications from logs. This may reduce verification costs and time-to-certification. However, the evidence does not include commercial adoption or productization details.
Next signals to watch include: publication in a peer-reviewed venue, release of the implementation or benchmark details, application to industrial case studies, and extensions to other timed logics or active learning settings. The completeness result may spur further theoretical work on passive learning for timed systems.